se p ,2008- v e r 2.0 n-channel enhancement mosfet ME20N03 01 parameter symbol limit unit drain-source voltage v dss 30 v gate-source voltage v gss 20 v t c =25 39 (note 1) continuous drain current t c =100 i d 25 a pulsed drain current i dm 100 a t c =25 37 maximum power dissipation t c =70 p d 24 w operating junction temperature t j -55 to 150 tQ10 sec 15 thermal resistance-junction to ambient (note 2) r ja steady state 45 /w thermal resistance-junction to case r jc 3.3 /w general description the ME20N03 is the n-channel logic enhancement mode power field effect transistors are produc ed using high cell density, dmos trench technology. this high density process is especially tailored to minimize on-state resistance. thes e devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching, and low in-line power loss are needed in a very small outline surface mount package. features r ds(on) Q 15m ? @v gs =10v r ds(on) Q 20m ? @v gs =4.5v super high density cell design for extremely low r ds(on) exceptional on-resistance and maximum dc current capability applications power management in desktop computer video graphic accelerate card battery powered system dc/dc converter pin configuration (to-252) top view absolute maximum ratings (t a =25 unless otherwise noted) note 1: bonding wire current limit note 2: the device mounted on 1in 2 fr4 board with 2 oz copper
se p ,2008- v e r 2.0 n-channel enhancement mosfet ME20N03 02 symbol parameter limit min typ max unit static v gs(th) gate threshold voltage v ds =v gs , i d =250 a 1 2 3 bv dss drain-source breakdown voltage v gs =0v, i d =250 a 30 v i gss gate-body leakage current v ds =0v, v gs =20v 100 na v ds =30v, v gs =0v 1 i dss zero gate voltage drain current v ds =30v, v gs =0v t j =55 5 a v gs =10v, i d = 15a 11 15 r ds(on) drain-source on-state resistance v gs =4.5v, i d = 15a 16 20 m v sd diode forward voltage i s =1a, v gs =0v 0.75 1.1 v dynamic ciss input capacitance 700 800 coss output capacitance 120 crss reverse transfer capacitance v ds =15v, v gs =0v, f =1mhz 35 pf rg gate resistance v ds =0, v gs =0v, f =1mhz 0.9 qg(4.5v) total gate charge v ds =15v, v gs =4.5v, i d =10a 11 14 qg(10v) total gate charge 20 26 qgs gate-source charge 5 qgd gate-drain charge v ds =15v, v gs =10v, i d =10a 4.9 nc t d(on) turn-on delay time 14 17 t r turn-on rise time 12 15 t d(off) turn-off delay time 43 55 t f turn-on fall time v ds =15v, r l =1.5 v gs =1a, r gen =3 r g =6 4 6 ns electrical characteristics (t a =25 unless otherwise specified)
se p ,2008- v e r 2.0 n-channel enhancement mosfet ME20N03 03 typical characteristics (t j =25 noted)
se p ,2008- v e r 2.0 n-channel enhancement mosfet ME20N03 04 typical characteristics (t j =25 noted)
se p ,2008- v e r 2.0 n-channel enhancement mosfet ME20N03 05 millimeters (mm) symbol min max a 2.00 2.50 a1 0.90 1.30 b 0.50 0.85 b1 0.50 0.80 b2 0.50 1.00 c 0.40 0.60 d 5.20 5.70 d2 6.50 7.30 d3 2.20 3.00 h 9.50 10.50 e 6.30 6.80 e2 4.50 5.50 l 1.30 1.70 l1 0.90 1.70 l2 0.50 1.10 l3 0 0.30 p 2.00 2.80 to-252 package outline
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